Informatics Publishing Limited

Jaymin Bhalani ¹, Dharmendra Chauhan ¹, Y. P. Kosta ², A. I. Trivedi ³

Affiliations
1 Electronics and Communication Engineering Department, Charotar University of Science and Technology, Changa, IN
2 Marvadi Institute of Technology, Rajkot, IN
3 Electrical Engineering Department, M.S. University, Baroda, IN

Abstract

In this paper, we propose two novel semi-blind channel estimation techniques based on QR decomposition for Rayleigh flat fading Multiple Input Multiple output (MIMO) channel using different receiver antenna combinations and various pilot symbols. In the first technique, the flat-fading MIMO channel matrix H can be decomposed as a upper triangular matrix R and a unitary rotation matrix Q as H=RQ. The matrix R is estimated blindly from only received data by using orthogonal matrix triangularization based house holder QR decomposition, while the optimum rotation matrix Q is estimated exclusively from pilot based Orthogonal Pilot Maximum Likelihood Estimator (OPML) algorithm. In the second technique, joint semi-blind channel and data estimation is performed using QR decomposition based Least Square (LS) algorithm. Simulations have taken under 4-PSK data modulation scheme for two transmitters and different combinations of receiver antennas as well as various training symbols. Finally, these two new techniques compare with Whitening Rotation (WR) based semi-blind channel estimation technique and results shows that those new techniques achieve very nearby performance with low complexity compare to Whitening rotation based technique. Also first technique with perfect R outperforms Whitening Rotation based technique.

Keywords

Multiple Input Multiple Output, Orthogonal Pilot ML Estimator, QR Decomposition, Semi Blind Channel Estimation.

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Kiritkumar Bhatt ¹, Saurabh M. Patel ¹, A. I. Trivedi ²

Affiliations
1 ECE Department, Sardar Vallahbai Patel Institute of Technology, IN
2 Electrical Engineering Department, M.S. University, IN

Abstract

Power has become an important aspect in the design of general purpose processors. Hence, to explore how design tradeoffs affect the power and performance of the processor. Proper implementation of pipelining structure at the architectural level may consume less power and help to improve the energy efficiency of the processor, and may dissipate less power for the same performance or higher performance for the same power. Some architectural changes, such as pipelining and caching, can significantly improve efficiency. Unfortunately many other architectural tradeoffs leave efficiency unchanged. This is because a large fraction of the energy is dissipated in essential functions and is unaffected by the internal organization of the processor. This paper discusses the design and implementation of power optimized parallel pipelined structures of 16-bit CPU on Xilinx Spartan-3E FPGA. A modified processor architecture is proposed to reduce the unnecessary switching activities to achieve significant power reduction.

Keywords

Processor Design, Embedded Processor, Low-Power Architecture, FPGA Implementation.

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Kiritkumar Bhatt ¹, A. I. Trivedi ²

Affiliations
1 ECE Department, SVIT – Vasad, Gujarat, IN
2 Electrical Engineering Department, M S University of Baroda, IN

Abstract

The FPGAs can be configured by the end-user to implement any digital system virtually, which may use millions of gates to be operated at few hundred MHz speed. Because of its reprogrammability, the FPGAs become very popular for the applications where prototyping and economic viability are of great concern. The state-of-the-art fabrication and manufacturing technologies are used to produce the current FPGAs, which comprise of high degree of integration and huge number of transistor count to make it suitable for today’s applications with high performance, but face a power consumption problem. Lower power consumption is a critical design issue in most embedded systems with CMOS technology, where logic switching is a significant factor affecting the system power consumption. The higher the switching frequency the larger the power consumed. This paper discusses the major power consumption sources in VLSI circuit with the primary focus on switching activity, its computation and its power estimation carried out by probabilistic approach.

Keywords

Power Estimation, Probabilistic Approach, Switching Activity, Low Power.

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Kiritkumar Bhatt ¹, A. I. Trivedi ¹

Affiliations
1 Department of Electrical Engineering, M S University of Baroda, Gujarat, IN

Abstract

To avail a longer battery life is a major constraint in the area of digital circuit design where complexity increases as per the Moore’s law. With the evolution of CMOS technology, it was believed that power consumption problem has been solved because static power consumption is very low and designers where focusing mainly on performance and area. But with the reasonable increase of device density per unit area the power consumption becomes considerably high. This is absolutely true for FPGAs, where power consumption noticeably rises due to the increase in the clock frequency, chip area and the ability to be programmed. FPGAs formed by three different technologies such as pure CMOS, Pass transistors and SRAM based. It becomes very popular because it takes very less development time, instant prototyping and less back end process. Hence, power consumption estimation and then optimisation has become very important. Looking to these facts this paper will explain the total power consumption model for CMOS based FPGAs because the power estimation is basic requirement for power optimized implementation on FPGAs.

Keywords

CMOS, FPGA, Optimization, Power Model.

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Jaymin Bhalani ¹, Dharmendra Chauhan ¹, A. I. Trivedi ²

Affiliations
1 Electronics and Communication Engg. Department, Charotar University of Science and Technology, Changa, IN
2 Electrical Engg. Department, M.S. University, Baroda, IN

Abstract

In this paper, we present Orthogonal Pilot MaximumLikelihood (OPML) based MIMO (Multi Input Multi Output) semi-blind channel estimation technique for quasi-static Rayleigh fading channel. Channel matrix H can be decomposed as the matrix product of a whitening matrix W and the unitary matrix Q , from which W can be estimated blindly using singular value decomposition of received output data and Q can be estimated exclusively from training sequences using OPML algorithm. Simulations taken for 2 transmitters and 4, 6 and 8 receiver antennas combination and different modulation schemes such as BPSK, 4-PSK and 8-PSK. Result shows that BER improvements in 8 receiver antennas and BPSK modulation scheme outperform others.

Keywords

Multi Input Multi Output, Orthogonal Pilot ML Estimator, Semi Blind Channel Estimation.

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